A bipolar transistor consisting of an emitter, a base, and a collector is typically created in a vertical arrangement from a monocrystalline semiconductor body having a pair of generally flat opposing surfaces. The emitter is located in the semiconductor material along one of the two surfaces, referred to here (for convenience) as the upper surface. The base is composed of an intrinsic base portion and one or two extrinsic base portions. The intrinsic base (portion) lies directly under the emitter. Each extrinsic base (portion) consists of a connection zone and a heavily doped contact zone which reaches the upper surface at a location laterally separated from the emitter. The connection zone provides an electrical path between the intrinsic base and the contact zone.
The main part of the collector is situated below the intrinsic base so that the emitter-to-collector current generally flows in the vertical direction. The collector also includes at least one heavily doped contact zone. A set of overlying electrical contacts to the emitter and to the various contact zones complete the transistor.
For future high-speed applications, the emitter and the intrinsic base need to be quite shallow. Also, the emitter needs to be close to the base contact zone(s), but not so close as to create a significant risk of an electrical short between the contacts. These objectives can be achieved with a manufacturing process in which the emitter is formed in a self-aligned manner by impurity outdiffusion from a doped non-monocrystalline semiconductor layer that later serves as the emitter contact. Electrically insulating spacers along the sides of the non-monocrystalline layer are used in creating the base contact zone(s) in a self-aligned manner. The sidewall spacers also help separate the base contact zone(s) from the non-monocrystalline layer.
In published European Patent Application No. 193,934, Iwasaki discloses how an NPN transistor is manufactured according to one version of the foregoing process. Iwasaki manufactures a P-channel insulated-gate field-effect transistor (FET) in conjunction with the NPN device. The two transistors are built from a monocrystalline silicon (sometimes simply "monosilicon") body that contains a pair of major N-type regions, referred to here as the first and second regions, spaced apart from each other along the upper surface of the body. The NPN transistor is formed from the first region. The second region is used for the P-channel FET.
Iwasaki provides an oxide layer along the upper surfaces of the two N-type regions. Boron is ion implanted into the first region through the oxide layer to convert a surface-adjoining portion into a primary P-type zone. Part of the P-type zone later serves as both the intrinsic base portion and the base connection zone. An emitter diffusion window is etched through the oxide down to the P-type zone.
A pair of patterned N-doped polycrystalline silicon (often simply "polysilicon") layers, referred to here as the first and second patterned layers, are created on parts of the oxide respectively overlying the first and second regions. Part of the polysilicon fills the emitter diffusion window. Iwasaki now provides oxide spacers along the sides of the patterned layers. At some point during the formation of the spacers and patterned layers, part of the N-type impurity in the first patterned layer diffuses through the window into the underlying monosilicon to convert a portion of the P-type zone into an N-type emitter for the NPN transistor. The first and second patterned layers serve respectively as the emitter contact for the NPN transistor and the gate electrode for the FET.
Boron is ion implanted into the major regions through selected parts of their upper surfaces to establish a surface-adjoining portion of the first region as a heavily doped P-type base contact zone for the NPN device and to establish a pair of surface-adjoining portions of the second region as heavily doped P-type source/drain (S/D) zones for the FET. The spacers and patterned layers act as an implantation shield (or mask) during this step.
Iwasaki's process is attractive because largely the same steps are used in fabricating both transistors. However, controlling the process variables so as to obtain good transistor characteristics from fabrication run to fabrication run presents a major problem for Iwasaki.
More specifically, the resistance of the extrinsic base portion of a bipolar transistor limits the switching speed and thus needs to be quite low. In Iwasaki's vertical NPN device, the extrinsic base resistance is highly dependent on the proximity of the emitter to the base contact zone. The distance between these two regions depends, in turn, on how much they diffuse laterally towards each other. Due to normal processing variations, it is quite difficult for Iwasaki to control the lateral diffusion in such a way as to achieve a low extrinsic base resistance without impairing other transistor properties.
The gate electrode of an insulated-gate FET needs to (vertically) overlap its source/drain zones slightly for the FET to perform well. Although not specifically discussed by Iwasaki, the requisite overlap for his P-channel FET is achieved through lateral diffusion of the same dopant used to create the base contact zone for the NPN transistor. This further complicates the control problem.
The extrinsic base resistance in Iwasaki's NPN transistor will, of course, be unduly high if the emitter and base contact zone are too far apart. Conversely, the emitter-base junction breakdown voltage will be undesirably low if the base contact zone gets too close to the emitter. The capacitance along the lateral periphery of the emitter-base junction (hereafter simply "emitter-base peripheral capacitance") increases significantly. This reduces the switching speed. Non-ideal transistor characteristics, such as tunneling, also arise when the spacing between the emitter and base contact zone is too little.
Scovell et al, published European Patent Application No. 199,061, discloses a slightly different technique for using emitter contact outdiffusion and oxide spacers to fabricate a vertical NPN transistor. The starting point in Scovell et al is a monocrystalline silicon substrate that contains a major N-type region located along the upper substrate surface. A thin silicon dioxide layer lies on the upper surface. Boron is implanted into the major region through part of the oxide layer to form a primary P-type zone, after which the oxide over the P-type zone is removed.
A patterned layer of polycrystalline silicon containing an N-type impurity is created on part of the upper surface of the P-type zone. The patterned layer is formed by depositing a blanket polysilicon layer on the upper surface of the structure, doping the blanket layer with the N-type impurity, and performing a dry etch to remove the entire thickness of portions of the blanket layer situated to the sides of the intended location for the emitter. Stopping the dry etch precisely at the upper surface of the substrate is extremely difficult. Some of the underlying monosilicon is invariably etched away. Scovell et al control the etch in such a way that less than 500 angstroms of monosilicon is removed.
Oxide spacers are provided along the sides of the remaining polysilicon, preferably by thermal oxidation. During the spacer formation, part of the N-type impurity in the polysilicon diffuses into the underlying monosilicon to form the emitter. Using the spacers and the patterned polysilicon as a mask, boron is implanted into the major region to create a pair of heavily doped P-type base contact zones. The remaining polysilicon is the emitter contact.
The dry etch into the monosilicon during the polysilicon patterning step in Scovell et al elevates the emitter with respect to the extrinsic base portions. The resultant decrease in the emitter-base peripheral parasitic capacitance acts to increase the transistor switching speed. However, the monosilicon etch also removes a great amount of the boron in the base connection zones. This increases the extrinsic base resistance substantially. Reproducibly controlling the transistor characteristics affected by the extrinsic base dopant profile is largely as much a problem as in Iwasaki.